1. Field of the Invention
The present invention relates to a bipolar transistor.
2. Description of Related Art
It is reported in an article by TAK. H. NING, RANDALL D. ISAAC, titled “Effect of Emitter Contact on Current Gain of Silicon Bipolar Devices”, IEEE Transactions on Electron Devices, November 1980, ED-27, No. 11, p 2051-2055 that change of a thickness of an emitter polysilicon changes a common emitter direct current amplification ratio (hereinafter abbreviated as hFE) in a non self-aligned homojunction bipolar transistor. More specifically, when the thickness of the emitter polysilicon is small, the ratio that holes flowing from a base to an emitter recombine with electrons decreases. Thus, a base current (hereinafter abbreviated as Ib) increases. However, there is no change in a collector current (hereinafter abbreviated as Ic). Further, as hFE=Ic/Ib is established, hFE decreases. If the emitter polysilicon has a large thickness to some extent, the ratio that the holes flowing from the base to the emitter recombine with the electrons increases. Thus, Ib becomes substantially constant. Thus, hFE becomes constant. Hence, a lower limit value of the thickness of the emitter polysilicon that is required to make hFE constant can be determined.
While the thickness of the emitter polysilicon increases, high-frequency property is degraded. For example, description will be made on cutoff frequency (hereinafter abbreviated as fT) which is the typical high-frequency property. According to an article by S. M. Sze, titled “Physics of Semiconductor Devices 2nd Edition”, John Wiley & Sons, Inc., 1981, p 158, fT is expressed by the following expressions (1) to (3).fT=1/(2πτec)  (1)τec=τE+τB+τC1+τC2  (2)τE=rE·(CE+CC+CP)  (3)
The main signals are as follows. τec indicates a total delay time. τE indicates a charging time of an emitter junction capacitance. τB indicates a charging time of a base. τC1 indicates a transport time through a collector depletion layer. τC2 indicates a collector junction charging time. rE indicates an emitter resistance. CE indicates emitter-base junction capacitance. CC indicates a base-collector junction capacitance. CP indicates other parasitic capacitance.
It is understood from the expressions (1) to (3) that, when the thickness of the emitter polysilicon becomes larger, rE increases and fT decreases. Accordingly, the upper limit value of the thickness of the emitter polysilicon can be determined from the value of rE and the property specification of the bipolar transistor.
Next, description will be made on bipolar transistors disclosed in Japanese Unexamined Patent Application Publication No. 2002-43321 and Japanese Unexamined Patent Application Publication No. 6-53229 as specific examples of the bipolar transistor. First, the structure of the bipolar transistor disclosed in Japanese Unexamined Patent Application Publication No. 2002-43321 will be described. FIG. 12 is a cross sectional view of the bipolar transistor disclosed in Japanese Unexamined Patent Application Publication No. 2002-43321. This bipolar transistor includes a base part, an emitter part, and a collector part.
In this bipolar transistor, as shown in FIG. 12, an N+ buried layer 102 is formed on a P− silicon substrate 101. An N− epitaxial growth layer 103 having a resistance ratio of 1 to 5 Ω·cm, and a thickness of 0.7 to 2.0 μm, and a recess field oxide silicon layer 104 are formed thereon, for example. Further, an interlayer insulation film 112 is formed thereon.
In the base part, a graft base region 108 and a base silicide layer 111a are formed in a part of the N− epitaxial growth layer 103. Further, a base electrode 114a that contacts with the base silicide layer 111a is formed by penetrating the interlayer insulation film 112.
In the emitter part, a P+ base region 105 and an N+ emitter region 109 are formed in a part of the N− epitaxial growth layer 103. An emitter part polysilicon layer 106 is formed thereon, and a side-wall oxide silicon layer 110 is formed outside thereof. In the upper part of the emitter part polysilicon layer 106, an emitter silicide layer 111b is formed. Further, an emitter electrode 114b that contacts with the emitter silicide layer 111b is formed by penetrating the interlayer insulation film 112.
In the collector part, a collector lead-out region 107 and a collector silicide layer 111c are formed on the N+ buried layer 102. Further, a collector electrode 114c that contacts with the collector silicide layer 111c is formed by penetrating the interlayer insulation film 112.
Next, a manufacturing method of this bipolar transistor will be described. FIGS. 13A to 13C are cross sectional views showing the manufacturing processes of the bipolar transistor. First, as shown in FIG. 13A, the N+ buried layer 102 is formed on the P− silicon substrate 101. Subsequently, the N− epitaxial growth layer 103 is grown thereon. Then, the recess field oxide silicon layer 104 is formed by thermal oxidation.
Next, as shown in FIG. 13B, after implanting phosphorus, thermal treatment is performed, so as to form the collector lead-out region 107. Subsequently, the P+ base region 105 is formed.
Next, polysilicon is deposited to have a thickness of 100 to 150 nm, and thereafter As ion is implanted. Thereafter, dry etching is performed using the resist as a mask, so as to form the emitter part polysilicon layer 106.
Further, BF2 ion is implanted using the emitter part polysilicon layer 106 as a mask. Subsequently, annealing is performed with an annealing temperature of 1000 to 1100° C. for 5 to 30 seconds. Thus, the graft base region 108 is formed, and As in the emitter part polysilicon layer 106 is diffused into the P+ base region 105, so as to form the N+ emitter region 109.
Next, the oxide silicon film is laminated by a CVD (Chemical Vapor Deposition) method. This oxide silicon film is shaped by dry etching, so as to form the side-wall oxide silicon layer 110.
Next, by sputtering, a refractory metal such as titanium is deposited. Subsequently, sintering is performed with a sintering temperature of 500 to 700° C. for 10 to 30 minutes, and makes the refractory metal react with the emitter part polysilicon layer 106, the graft base region 108, and the collector lead-out region 107, so as to form the base silicide layer 111a, the emitter silicide layer 111b, and the collector silicide layer 111c. The unreacted refractory metal is removed by wet etching.
Then, as shown in FIG. 13C, the interlayer insulation film 112 below the first-layer aluminium wiring (not shown) is formed, and the surface is planarized. Thereafter, a base contact opening 113a, an emitter contact opening 113b, and a collector contact opening 113c are formed.
Next, the base electrode 114a, the emitter electrode 114b, and the collector electrode 114c are formed, and the bipolar transistor as shown in FIG. 12 is thus manufactured.
Next, the structure of the bipolar transistor disclosed in Japanese Unexamined Patent Application Publication No. 6-53229 will be described. FIG. 14 is a cross sectional view of the bipolar transistor disclosed in Japanese Unexamined Patent Application Publication No. 6-53229. As shown in FIG. 14, this bipolar transistor has an N+ buried layer 202 formed on a P− silicon substrate 201. An N− epitaxial growth layer 203 and an element isolation oxide film 204 are formed thereon. Further, a P+ base region 206 and an intrinsic base 209 are formed on the N− epitaxial growth layer 203. An N+ emitter region 211 is formed in a part of the intrinsic base 209.
A P+ polysilicon 205 is formed on the element isolation oxide film 204 and the P+ base region 206. An N+ polysilicon layer 212 is formed on the N+ emitter region 211. Further, a polysilicon layer 210 is formed to contact with the N+ polysilicon layer 212, and an oxide film 207 is further formed outside thereof. A nitride film 208 is formed in a part on the oxide film 207.
Further, a tungsten layer 213 that covers the nitride film 208 and the N+ polysilicon layer 212 is formed. Then, an oxide film 214 that covers the upper surface of the bipolar transistor is formed. Furthermore, an electrode 215 that contacts with the tungsten layer 213 is formed by penetrating the oxide film 214.
Next, a manufacturing method of the bipolar transistor will be described. FIGS. 15A to 15C are cross sectional views showing the manufacturing processes of the bipolar transistor. First, as shown in FIG. 15A, the N+ buried layer 202 is formed on the P− silicon substrate 201. The N− epitaxial growth layer 203 is grown thereon. Subsequently, the element isolation oxide film 204 is formed.
Next, the P+ polysilicon 205 is formed. After that, thermal treatment is performed, so as to diffuse P impurities in the P+ polysilicon 205 into the N− epitaxial growth layer 203 and form the P+ base region 206. Further, by the CVD method and anisotropic dry etching, the oxide film 207 and the nitride film 208 are formed, and the N− epitaxial growth layer 203 is exposed. Then, treatment is performed in gas atmosphere including P doping gas, so as to form the intrinsic base 209 in a part where the N− epitaxial growth layer 203 is exposed.
Next, as shown in FIG. 15B, oxide film etching, polysilicon depositing, and anisotropic dry etching are performed, so as to form the polysilicon layer 210. Subsequently, treatment is performed in the gas atmosphere including N doping gas, and thus the N+ emitter region 211 is formed in a part where the intrinsic base 209 is exposed.
Next, as shown in FIG. 15C, the N+ polysilicon layer 212 having a thickness of about 100 nm is formed using gas including N doping gas. Subsequently, the tungsten layer 213 is formed by selective growth. Then, the oxide film 214 is formed on the tungsten layer 213. Thereafter, by a known method, the oxide film 214 is opened to form the electrode 215, so as to obtain the bipolar transistor shown in FIG. 14.